YVONNE GONZALEZ ROGERS, District Judge.
Defendant Freescale Semiconductor, Inc. ("Freescale") has asserted, as an affirmative defense and as a cross-claim, the invalidity of the patents at issue based upon obviousness. Plaintiff MediaTek, Inc. ("MediaTek") filed its Motion for Summary Judgment on the grounds that the asserted claims of U.S. Patent No. 6,738,845 ("the `845 patent") are not invalid as obvious under United States Code Title 35, section 103(a). (Dkt. No. 298.) First, MediaTek argues that the prior art references fail to disclose all limitations of the two asserted `845 claims (independent claims 1 and 21 and the claims depending therefrom), whether considered alone or in combination. Second, MediaTek contends that Freescale's proposed combinations fail for the independent reason that Freescale has failed to show how or if the two references could be combined to form an operable system.
Simultaneously, and by separate motion, MediaTek also moved to strike portions of Freescale's expert reports which relied on references not identified in Freescale's Patent Local Rule 3-3 invalidity contentions, including those portions of the reports that were offered as evidence in support of Freescale's obviousness defense. (Dkt. No. 296.) The Court's Order on the motion strike, granting in part the request to strike portions of the expert report submitted by Dr. Frank Vahid ("Vahid"), was entered February 21, 2014. (Dkt. No. 454, "Order Striking Portions of the Vahid Report.")
Having carefully considered the papers submitted, the admissible evidence, and the pleadings in this action, and for the reasons set forth below, the Court hereby
Freescale has asserted invalidity of MediaTek's patent claims on account of obviousness, both as an affirmative defense and as a cross-claim. Freescale therefore bears the burden of persuasion on these issues at trial. Otsuka Pharm. Co., Ltd. v. Sandoz, Inc., 678 F.3d 1280, 1290 (Fed. Cir. 2012) cert. denied, 133 S.Ct. 940 (2013). As the party challenging a patent claim's validity, Freescale must prove its case by clear and convincing evidence. Id. A mere preponderance of evidence is not enough; rather, the evidence must engender an abiding conviction that it is highly probable that the claims are invalid. See Pfizer, Inc. v. Apotex, Inc., 480 F.3d 1348, 1360 n5 (Fed. Cir. 2007). On summary judgment evidence is viewed in the light most favorable to the non-moving party. Anderson v. Liberty Lobby, Inc., 477 U.S. 242, 252 (1986). However, the Court must bear in mind the standard of proof applicable to the claims in deciding whether summary judgment is warranted.
Claims of an issued patent are presumed valid. Bausch & Lomb, Inc. v. Barnes-Hind/Hydrocurve, Inc., 796 F.2d 443, 446 (Fed. Cir. 1986) (citing 35 U.S.C. § 282). A patent claim is invalid as obvious "if the differences between the subject matter sought to be patented and the prior art are such that the subject matter would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains." 35 U.S.C. § 103(a). Whether prior art renders a patent claim obvious is a question of law that relies on underlying factual findings. Otsuka Pharm. Co., Ltd. v. Sandoz, Inc., 678 F.3d 1280, 1290 (Fed. Cir. 2012) cert. denied, 133 S.Ct. 940 (2013). The factual issues to consider in the obviousness analysis include: (1) scope and content of the prior art; (2) applicable level of ordinary skill in the art; (3) differences between the claimed invention and the prior art; and (4) secondary indicia of obviousness or non-obviousness. Unigene Labs., Inc. v. Apotex, Inc., 655 F.3d 1352, 1360 (Fed. Cir. 2011) (citing Graham v. John Deere Co., 383 U.S. 1, 17-18 (1966)).
Where obviousness is claimed to be established by more than one reference in combination, it requires more than a showing that the prior art contains separate references covering each separate limitation in a claim under examination, but rather that a person of ordinary skill at the time of the invention would have selected and combined those prior art elements in the normal course of research and development. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 418, 421. (2007); Unigene Labs., Inc. v. Apotex, Inc., 655 F.3d 1352, 1360 (Fed. Cir. 2011). "[T]he Federal Circuit has employed a `teaching, suggestion, or motivation' (TSM) test, under which a patent claim is only proved obvious if the prior art, the problem's nature, or the knowledge of a person having ordinary skill in the art reveals some motivation or suggestion to combine the prior art teachings." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 399 (2007). To find that elements of two references would have been combined by a person of ordinary skill in the art ("POSITA"), the references must themselves contain some teaching, suggestion, or motivation to make the combination. Ashland Oil, Inc. v. Delta Resins & Refractories, Inc., 776 F.2d 281, 297 n.24 (Fed. Cir. 1985), cert. denied, 475 U.S. 1017 (1986).
For purposes of determining obviousness, a POSITA is "presumed to be one who thinks along the line of conventional wisdom in the art and is not one who undertakes to innovate, whether by patient, and often expensive, systematic research or by extraordinary insights." Standard Oil Co. v. Am. Cyanamid Co., 774 F.2d 448, 454 (Fed. Cir. 1985). To the extent that references "teach away" from the patent claims at issue, they cannot establish obviousness. McGinley v. Franklin Sports, Inc., 262 F.3d 1339, 1354 (Fed. Cir. 2001).
References that, in combination, would produce a "seemingly inoperative device," are held to "teach away" from obviousness of that combination. McGinley, 262 F.3d at 1354, citing In re Sponnoble, 405 F.2d 578, 587 (Cust. Pat. Appeals, 1969), and In re Gordon, 733 F.2d 900, 902 (Fed.Cir. 1984). In other words, there is no motivation to modify a prior art device if one of ordinary skill would have believed the modification could disrupt the functioning of the prior art device itself. Gordon, 733 F.2d at 902; In Re Fritch, 972 F.2d 1260, 1265-66 (Fed. Cir. 1992); Applied Materials, Inc. v. Adv. Semiconductor Mat'ls Am., Inc., C-92-20643 RMW, 1995 WL 848951 at *13 (N.D. Cal. Nov. 1, 1995). Thus, a party seeking to establish obviousness must show that a POSITA would have had a "reasonable expectation of success" in combining the prior art references proffered. Allergan, Inc. v. Sandoz Inc., 726 F.3d 1286, 1292 (Fed. Cir. 2013) cert. denied, 134 S.Ct. 1764 (2014).
MediaTek moves for summary judgment as to Freescale's claims of invalidity due to obviousness with respect to independent Claim 1 and dependent Claims 2 and 5 of the `845 Patent. Claim 1 of the `845 patent recites, in part:
(`845 Patent, 9:58-60, 10:32-39 [quoted portions italicized in note].)
Claim 1's DMA controllers perform a discrete function: moving data from one location to another (the first and second slave subsystems) so that processor time is not taken up performing this task. (SUMF Fact 2.) With a DMA controller, a system can perform data management tasks, thereby freeing up the processor to perform other operations. (SUMF Fact 5.)
Freescale asserts in its invalidity contentions that Claim 1 is obvious based upon a combination of prior art, referenced by the parties as "Bhuyan" and "Bowes856." (SUMF Fact 10.) In opposition to the instant motion, Freescale, through its expert Vahid, contends that: (1) it would have been obvious for a POSITA to have substituted a particular type of DMA, depicted in Figure 1A of Bowes856 and called a "fly-by DMA," for one of the multiple processors taught in Bhuyan, and (2) the result would contain all of the elements of claim 1's invention. (Id., Vahid Report, ¶¶ 94-105, Exh. D-1, D-3.) Vahid's report states that a POSITA in 1998 would have seen that the crossbar switch in Bhuyan was a module interconnection network where: (1) multiple masters could access multiple slaves in a bus architecture; (2) each master and each slave had its own associated bus; and (3) arbitration modules associated with each slave determined access to that slave independent from the other arbitration modules. (Vahid Opening Report, Dkt. No. 298-11, ¶ 96.) Vahid further opines that it was within the level of skill in the art at that time to add, from Bowes856, a DMA controller to allow slave-to-slave access and communications over the crossbar switch, relieving the other processors of that duty. (Id. at ¶¶ 96 and 99.) Thus, it is Vahid's opinion that Bhuyan in combination with Bowes856 teaches everything in Claim 1, as well as dependent claims 2 and 5. (Id. at ¶ 99.) Vahid's report refers specifically to Bowes856's description, in its Figure 1A, of a "typical prior art fly-by DMA scheme ... [which] manages the data transfer, [but] the data does not pass through the DMA controller." (Vahid Report Exh. D-1 at p.14.)
First, the Court has stricken key portions of Vahid's Report which Freescale relies upon for its obviousness argument. As the Court found in its Order Striking Portions of the Vahid Report, Freescale never mentioned in its invalidity contentions the "fly-by DMA scheme" illustrated in Figure 1A of Bowes856, but instead only cited to Figure 2A. (See also SUMF 21 and response thereto [conceding that Figure 1A was not disclosed, just Figure 2A].) The reference to Figure 1A in the Vahid Report was stricken due to Freescale's failure to conform Vahid's Report to its invalidity contentions as required by Patent L.R. 3-3(c) ("identify[] specifically where each limitation of each asserted claim is found within each Accused Instrumentality.") Thus, any evidence touching on the DMA controller from Figure 1A to Bowes856 cannot be used to meet Freescale's burden to prove obviousness.
At the supplemental hearing concerning the effect of the Court's Order Striking Portions of the Vahid Report on the instant motion, Freescale argued that it could nevertheless establish obviousness with those remaining portions of Vahid's Report which reference the Abstract portions of Bowes856, generally describing a generic DMA controller. (Transcript, February 28, 2014 Hearing, Dkt. No. 471, at 90:6-93:5.)
Reference to the background/Abstract sections of the Bowes856, which only discuss the general purpose of DMA controllers, is insufficient to meet the claim limitations. Indeed, MediaTek's argument reveals that the invention of Bowes856 was not the prior art reference Vahid suggested would make the patent-in-suit obvious, but was merely a placeholder reference for the generic concept of "a DMA controller." While Vahid purported to identify a specific combination of prior art that would satisfy the requirements of Claim 1, all he did was describe a generic DMA "dropped in the processor block" of the system described in the Bhuyan reference, without any particular consideration of the characteristics of that DMA subsystem. (See Hearing Transcript, December 17, 2013 hearing, Dkt. 385, 15:20-16:1.) As MediaTek's expert, Dr. Krste Asanovic pointed out in his report, Vahid never specified which embodiment from Bowes856 satisfies Claim 1's requirement of a DMA subsystem "comprising a DMA controller coupled to a third bus as a third bus master." (Asanovic Rebuttal Report, Dkt. No. 298-9, at ¶53.)
Claim 1 requires a "DMA controller" that is able to transfer data between two slave subsystems "via the third bus," over which it is master. (SUMF Fact 11.) To show obviousness, the evidence must demonstrate that all the requirements of Claim 1 would be met. It is undisputed that the Bhuyan reference does not mention a DMA or any processor that could act as the claimed DMA controller at all. (SUMF 22-25 and response thereto.) Thus, to establish obviousness the Bowes 856 reference must disclose a DMA controller possessing these characteristics. With nothing more than the reference to the Bowes 856 Abstract left for Freescale to rely upon, it cannot meet its burden.
Moreover, MediaTek has demonstrated that Freescale cannot meet its burden to show obviousness because its expert never considered whether the combination of the references from Bhuyan and Bowes856 would be operable. (See SUMF 13.) MediaTek's expert, Asanovic, submitted evidence that the proposed combination of Bhuyan and Bowes856 would not result in an operable system because: (1) the combination does not explain how the DMA would communicate with the processors, meaning the DMA would never execute any data transfers; and (2) additional inventive steps would be required to create a bus that supports transferring data between two slaves. (Asanovic Rebuttal Report ¶¶ 67, 68.)
Freescale's opposition is two-fold. First, Freescale argues that, as a matter of fact, Vahid's opinion establishes that a POSITA would know how to connect a "DMA controller" to the system of Bhuyan such as would allow it to transfer data between two slave subsystems "via the third bus," as required by Claim 1. Vahid has opined that "a person of ordinary skill in the art would know how to either program one of the processors in Bhuyan with DMA capability or replace one of the processors in Bhuyan with a DMA controller from Bowes856 in order to create the claimed invention." (Oppo., Dkt. 321-5, at 9:8-12, citing Vahid Depo. Tr. 319:13-320:8 [Dkt No. 321-14], and Vahid Opening Report ¶¶ 96-98, Ex. D at 4-6, 34-36.) Second, as a matter of law, Freescale asserts that, once it has offered evidence that a proposed combination meets the limitations of the claims, the burden shifts to MediaTek to establish nonobviousness, and evidence of teaching away merely creates a material factual dispute that precludes summary judgment. (Oppo. at 8:23-9:4.)
As to the applicable law, Freescale misstates the burdens at issue. A patent is presumed valid and the challenger has the burden of establishing invalidity by clear and convincing evidence. Pfizer, Inc. v. Apotex, Inc., 480 F.3d 1348, 1360 (Fed. Cir. 2007). Even if a prima facie case is established, and the patentee is called upon to provide rebuttal evidence, "the presumption of validity remains intact and the ultimate burden of proving invalidity remains with the challenger throughout the litigation." Pfizer, Inc. v. Apotex, Inc., 480 F.3d 1348, 1360 (Fed. Cir. 2007) (citing cases). "The trial court has the responsibility to determine whether the challenger has met its burden by clear and convincing evidence by considering the totality of the evidence, including any rebuttal evidence presented by the patentee." Id.
Turning to the facts, the evidence offered by MediaTek shows that Freescale did not consider whether a POSITA would have had a "reasonable expectation of success" in combining the prior art references proffered or if, instead, inoperability would teach away from the patent. Allergan, 726 F.3d at 1292. Vahid testified that he had not considered whether any particular combination — that is, Bhuyan and any particular kind of DMA controller meeting the requirements of Claim 1 — would be functional. (See SUMF 13 and response thereto.) Vahid testified that he did not perform "an analysis of the detailed steps for a particular system," acknowledging that the conceptual design of combining a "multiprocessor network system with a DMA" was very different from determining whether a specific system would work, since "in design, the devil is in the detail." (Hammon Decl., Exh. 3 [Dkt. No. 298-14], Vahid Depo. Tr., at 315:12-316:2.) In short, Freescale offers no admissible evidence to dispute MediaTek's evidence that the combination here would be inoperable and would teach away from the obviousness of the claims. In the absence of contrary evidence, there is no triable issue. Thus, even if the evidence offered by Freescale had not been stricken, it was insufficient to create a triable issue, particularly under a "clear and convincing" standard.
As a result, Freescale has failed to meet its burden to show that it has sufficient evidence to support its claim of invalidity based upon obviousness. MediaTek's motion for summary judgment on the issue of obviousness of Claims 1, 2, and 5 of the `845 Patent is
MediaTek next moves for summary judgment as to the claimed invalidity of independent Claim 21 and dependent Claims 22 and 25 based on a combination of Bhuyan and another Bowes reference, Bowes547. Claim 21 recites a multiprocessor system that accomplishes bus arbitration through a particular component, called a "Bus Arbitration Module" (BAM). The BAM must enable "first and second data processing subsystems to access different ones of the first and second slave subsystems at the same time" and must be "further configured and arranged" such that, when "all requests for access" to one of the slave subsystems "are of the same priority level," one of the "data processing subsystems is guaranteed to have access to a greater portion of the available bandwidth" than the other. (`845 Patent, 12:76-13:38, quoted portions italicized in note.)
Freescale's obviousness theory is based upon Vahid's expert opinion that a single combination of two references renders claims 21, 22, and 25 of the `845 patent obvious: (1) the Bhuyan reference together with (2) the Bowes547 patent. (SUMF Facts 30, 45.) Vahid purports to arrive at the inventions claimed in claims 21, 22, and 25 by combining the Figure 3 and Figure 5 embodiments from Bhuyan with Bowes547. (SUMF Fact 45.) Specifically, Vahid contends that it would have been obvious to a POSITA that the bus arbitration scheme of Bowes547 could have been combined with the bus architecture of Bhuyan to arrive at the claimed invention. (SUMF Fact 30.)
As a preliminary matter, Vahid's reliance on Bhuyan Figure 5 has been stricken. (See Order Striking Portions of the Vahid Report at 6:3-18.) More specifically, the Court found that Freescale did not disclose its intention to rely on Bhuyan Figure 5 in connection with any claims in the `845 Patent. Consequently, Vahid's references to Figure 5, in the body of the report, as well as in Exhibits D-2 (on Claims 1, 2, and 5) and Exhibit D-4 (on Claims 21, 22, and 25), were improper and cannot be considered evidence in opposition to the summary judgment motion.
In addressing the obviousness claim, Vahid's Opening Report, Paragraph 109 states:
(Vahid Opening Report, Dkt. No. 298-11, at 26, emphasis supplied.) Thus, Vahid did not opine that Exhibit D-2 alone demonstrates that Bhuyan combined with Bowes 547 teaches all the limitations of Claims 21, 22, and 25.
MediaTek first argues that Freescale's obviousness theory fails as a matter of law because Bhuyan and Bowes547, alone or in combination, fail to teach all the limitations of claims 21, 22, and 25. The parties agree that the combination of references must cover all of the following limitations:
Vahid opines that the Bhuyan and Bowes 547 references, along with the knowledge and creativity of a POSITA, disclose all the limitations of Claims 21, 22, and 25. Essentially, Freescale contends that Bhuyan provides the BAM and Bowes547 provides the features/limitations required of that BAM to meet Claims 21, 22, and 25. More specifically, Vahid posits that the collection of memory arbiters and the cross bar switch network from Bhuyan constitute the BAM, and that they could carry out the arbitration scheme set forth in Bowes547, assuming a POSITA of sufficient skill to "program or create a dedicated processor for the arbiter in Bhuyan," by editing software code to implement Bowes547 in Bhuyan's system. (Vahid Report ¶108.) Vahid opines that a "person of ordinary skill would also have known how to modify the software code to implement a desired bandwidth of one processor with respect to another." (Vahid Report ¶ 108.)
MediaTek argues that Freescale's expert report is inadequate to meet its burden of clear and convincing evidence that each of the limitations of the claims is met by the combination of references offered. The Court agrees.
The combination of references must meet all the limitations of the claim, including: (1) enabling "access [to] different ones of the first and second slave subsystems at the same time;" and (2) allocating "a greater portion of the available bandwidth" to one data subsystem over another when receiving requests at the same priority. As MediaTek's expert explains, the Bhuyan reference only teaches a mathematical model in which processor requests to a memory/slave subsystem are uniformly distributed among memory partitions. (SUMF Fact 38.) Such a model is contrary to a bus arbitration scheme favoring one data processing subsystem over another. (SUMF Fact 39.) Indeed, the Bhuyan reference's assumption of equal treatment of memory partitions actually teaches away from this requirement. Moreover, neither Bhuyan nor Bowes547 discloses a method or algorithm for deciding among requests of the same priority level for access to two different slave subsystems at the same time where the allocation would favor one processor over another. Although Bowes547 has an arbiter, it arbitrates among components that share a single memory bus. (SUMF Fact 41.) Vahid's Report implicitly acknowledges gaps in the references, indicating that a POSITA would have to modify the code to create the dedicated processor for the arbiter and to implement the bandwidth-favoring limitation. (Vahid Report at ¶108.) Thus, neither reference, nor their combination would meet all the limitations of Claim 21, making summary judgment in favor of MediaTek appropriate on Freescale's obviousness theory.
Furthermore, even if Freescale had met its burden to show that the combination meets the claim limitations, Freescale has not offered evidence that it considered whether the system resulting from the proposed combination of Bhuyan and Bowes547 would be operable.
MediaTek moves for summary judgment based on evidence from its expert, Asanovic, that significant modifications would be required to modify the arbiter from Bowes547 to work for a larger number of processors, as in the system of Bhuyan. (Asanovic Report at ¶ 103.) While Vahid acknowledges that there would need to be coding to combine the system of Bhuyan with the arbiter of Bowes547, he does not discuss all the modifications that would be necessary, such as reassigning processors and rewriting the logic of the arbitration system from what is stated in Bowes547. (Id.) Asanovic further asserts that "[n]one of this would be obvious or trivial to a person of ordinary skill in the art, and Dr. Vahid has not shown how it could be done." (Id.) Asanovic therefore concludes that there is no reasonable expectation of success in combining Bhuyan's BAM with Bowes547's arbitration scheme to yield an operable system that meets all the elements of the claims. (Id. at ¶¶ 105, 106.)
In opposition, Freescale merely offers Vahid's opinion that it is possible to combine the references and that a POSITA would have been motivated to do so. (Vahid Report ¶¶ 108, 111.) Vahid's Report is entirely too conclusory to create a genuine factual dispute. "[C]onclusory statements of counsel or a witness that a patent is invalid do not raise a genuine issue of fact." Biotec Biologische Naturverpackungen GmbH & Co. KG v. Biocorp, Inc., 249 F.3d 1341, 1353 (Fed. Cir. 2001) (citing cases). Simply arguing against MediaTek's facts in a summary manner, without evidence to establish a dispute, does not suffice.
More significantly, Freescale does not address the key issue here, as it offers no evidence that the combination would be operable, or that it even considered whether the combination would have appeared operable, to a POSITA. In his deposition, Vahid stated that he could "only answer that as a conceptual design, in which case one simply would need to plug in the priority scheme of Bowes into whatever priority scheme previously existed in the Bhuyan system to get that working." (SUMF Fact 46.) At best, Vahid has offered opinions that a POSITA at the time "would have seen" that the two references could have been combined (¶ 108) and "would have known how to modify" the Bowes547 reference to meet the requirements of the Claims at issue here. (Id.)
As a consequence, Freescale has failed to meet its burden to show that it has sufficient evidence to support its claim of invalidity based upon obviousness on either ground discussed. MediaTek's motion for summary judgment on the issue of obviousness of Claims 21, 22, and 25 of the `845 Patent is, therefore,
Based upon the foregoing, Freescale has failed to offer evidence sufficient to create a triable issue as to its claim of invalidity of the `845 Patent on grounds of obviousness. Consequently, MediaTek is
This order terminates the underlying motion at Docket No. 298.
a first data processing subsystem comprising a first processor coupled to a first bus as a first bus master;
a second data processing subsystem comprising a second processor coupled to a second bus as a second bus master;
a direct memory access (DMA) subsystem comprising a DMA controller coupled to a third bus as a third bus master;
a first slave subsystem comprising a memory unit coupled to a fourth bus;
a second slave subsystem comprising a fifth bus;
a first arbitration unit associated with the first slave subsystem, having each of the first, second, third and fourth busses coupled thereto, configured and arranged to arbitrate among at least the first data processing subsystem, the second data processing subsystem, and the DMA subsystem for access to the first slave subsystem, and to couple the fourth bus to any selected one of at least the first, second, and third busses so as to enable a selected one of at least the first data processing subsystem, the second data processing subsystem, and the DMA subsystem to access the first slave subsystem; and
a second arbitration unit associated with the second slave subsystem, having each of the first, second, third and fifth busses coupled thereto, configured and arranged to arbitrate among at least the first data processing subsystem, the second data processing subsystem, and the DMA subsystem for access to the second slave subsystem, and to couple the fifth bus to any selected one of at least the first, second, and third busses so as to enable a selected one of at least the first data processing subsystem, the second data processing subsystem, and the DMA subsystem to access the second slave subsystem;
wherein each of the first and second arbitration units is configured and arranged to operate independently such the first arbitration unit can enable anyone of the first data processing subsystem, the second data processing subsystem, and the DMA subsystem to access the first slave subsystem at the same time that the second arbitration unit enables any other of the first data processing subsystem, the second data processing subsystem, and the DMA subsystem to access the second slave subsystem; and
wherein the DMA subsystem is configured and arranged such that, when the first and second arbitration units enables the DMA subsystem to access each of the first and second slave subsystems, the DMA controller can cause data to be transferred between the first slave subsystem and the second slave subsystem via the third bus.
A system, comprising:
a first data processing subsystem comprising a first processor coupled to a first bus as a first bus master;
a second data processing subsystem comprising a second processor coupled to a second bus as a second bus master;
a first slave subsystem comprising a memory unit coupled to a third bus;
a second slave subsystem comprising a fourth bus; and a bus arbitration module (BAM), having the first, second, third, and fourth busses coupled thereto, configured and arranged to couple each of the third and fourth busses to any selected one of at least the first and second busses so that each of first and second slave subsystems can be independently accessed by either of the first and second data processing subsystems, thereby enabling the first and second data processing subsystems to access different ones of the first and second slave subsystems at the same time, the BAM being further configured and arranged to employ an arbitration scheme for access to at least a first one of the first and second slave subsystems in which, during any period when all requests for access to the first one of the first and second slave subsystems are of the same priority level, a first one of the first and second data processing subsystems is guaranteed to have access to a greater portion of the available bandwidth of the first one of the first and second slave subsystems than is a second one of the first and second data processing subsystems.