CLAIMS CONSTRUCTION ORDER (Re: Docket No. 74)

PAUL S. GREWAL, Magistrate Judge.

In this patent infringement suit, Plaintiff SynTest Technologies, Inc. alleges that Defendant Cisco Systems, Inc. infringes U.S. Patent Nos. 7,007,213, 7,434,126 and 7,779,323. The parties submitted ten claim construction disputes from those asserted patents for resolution by the court. The court issued a summary construction order a few days after the hearing and explained that a more complete order would follow providing the court's reasoning.1 The court now provides that reasoning.

I. BACKGROUND

A. The Parties

SynTest and Cisco are California corporations with principal places of business in this district.2 SynTest creates and licenses tools for the design of application specific integrated circuits ("ASICs"). SynTest is the assignee of each of the asserted patents. Cisco is a former SynTest customer. SynTest alleges Cisco developed and uses ASICs practicing the patents-in-suit without a valid license.3

B. The Technology

1. Fault Testing the Logic of an Integrated Circuit

Before an ASIC can be manufactured, its logic must first be tested to see if it works as intended. Testing tools can be built into an AISC that work either with external automatic test equipment or alone. Testing tools built into the circuit itself are collectively known as a Built-In Self-Test.

ASICs commonly contain millions of "flip-flops" that act as memory cells. A flip-flop stores states of logic as a one or zero. The state of a flip-flop is controlled by electronic pulses that run through the ASIC. The frequency of these pulses is in turn controlled by a clock. The area of an ASIC controlled by a clock is called a clock domain. A single ASIC can have dozens of such domains — each controlled by separate clocks operating at different frequencies.

2. Design For Test Techniques

Logic faults include "stuck-at" faults and "delay" faults. With a stuck-at fault, the state of the flip-flop is stuck at one or zero. A delay fault is one that causes the ASIC to operate slower than expected. The three patents in this case share a common specification and are directed to a specific design for test ("DFT") technique for detecting whether the logic in an ASIC suffers from any other type of fault. The asserted patents describe DFT techniques "that can facilitate detection or location of physical defects that can manifest themselves as logic faults within an integrated circuit or circuit assembly."4

The particular scan design at issue in the asserted patents involves loading (or "shifting") test patterns into storage elements of an ASIC using clock pulses known as "shift clock pulses."5 When an ASIC receives the shift clock pulses and is operating in what is called "scan mode," the ASIC reacts by shifting the test stimuli into the ASIC's storage elements. Next, when the ASIC is operating in what is called "normal mode" and receives "capture clock pulses,"6 those pulses cause the ASIC to operate on the loaded test stimuli as it would when operating in its normal functional mode.7 Finally, when the ASIC is returned to scan mode and it receives additional shift clock pulses, the shift clock pulses are applied to collect or "shift out" of the storage elements the results of the circuit's operation, so that they can be analyzed.

3. Detecting Faults Within and Crossing Clock Domains

An "integrated circuit or circuit assembly, in general, contains two or more system clocks, each controlling one module, or logic block, called [a] clock domain."8 In other words, a "clock domain" is a module or logic block of an ASIC that is controlled by a single system clock. The system clock is the clock that drives the normal functional operation of the clock domain. ASICs can experience logic faults that occur completely "within" a given clock domain, as well as faults that "cross" multiple clock domains.9 One aspect of the invention claimed in the asserted patents is the ability to detect both faults within and faults crossing any two clock domains.10

C. The Independent Asserted Claims

1. Claim 1 of the '213 Patent

Independent claim 1 of the '213 patent provides:

1. A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly during self-test, where N>I, each clock domain having one or more capture clocks and one or more scan cells, each capture clock comprising a selected number of shift clock pulses and a selected number of capture clock pulses, each shift clock pulse comprising a clock pulse applied in scan mode, each capture clock pulse comprising a clock pulse applied in normal mode; said method comprising the steps of:

2. Claim 1 of the '126 Patent

Independent claim 1 of the '126 patent provides:

1. A computer-aided design (CAD) method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test and selftest mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a selected number of shift clock pulses and a selected number of capture clock pulses, each shift clock pulse comprising a clock pulse applied in scan mode, each capture clock pulse comprising a clock pulse applied in normal mode, said CAD method comprising the computer-implemented steps of:

3. Claim 1 of the '323 Patent

Independent claim 1 of the '323 patent provides:

1. An apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said apparatus comprising:

II. LEGAL STANDARDS

Almost nine years after the Federal Circuit's seminal Phillips decision,14 the canons of claim construction are now well-known — if not perfectly understood — by parties and courts alike. "To construe a claim term, the trial court must determine the meaning of any disputed words from the perspective of one of ordinary skill in the pertinent art at the time of filing."15 This requires a careful review of the intrinsic record, comprised of the claim terms, written description, and prosecution history of the patent.16 While claim terms "are generally given their ordinary and customary meaning," the claims themselves and the context in which the terms appear "provide substantial guidance as to the meaning of particular claim terms." Indeed, a patent's specification "is always highly relevant to the claim construction analysis."17 Claims "must be read in view of the specification, of which they are part."18 Although the patent's prosecution history "lacks the clarity of the specification and thus is less useful for claim construction purposes," it "can often inform the meaning of the claim language by demonstrating how the inventor understood the invention and whether the inventor limited the invention in the course of prosecution, making the claim scope narrower than it would otherwise be."19 The court also has the discretion to consider extrinsic evidence, including dictionaries, learned treatises, and testimony from experts and inventors.20 Such evidence, however, is "less significant than the intrinsic record in determining the legally operative meaning of claim language."21

III. DISCUSSION

A. Dispute #1: Whether the Preamble to Claim 1 of the '126 Patent is Limiting

The parties dispute whether the claim preambles are limiting with respect to the '213 patent (claims 1 and 29), the '126 patent (claim 1) and the '323 patent (claim 1).

Although SynTest believes the question does not constitute a claim construction issue, it argues in the alternative that not all of the preambles are limiting. Because language in the preambles is repeated in the claim terms or referenced elsewhere in the patent, many of the ideas in the preambles necessarily will be addressed in other portions of the construction and there is no reason for the court to construe them within the preamble. SynTest does recognize one exception: the preamble to claim 1 of the '126 patent. The reason is that limitations A through E of that claim merely describe performing tasks on a circuit and limitations from the preamble are necessary for these later limitations to have meaning.22 In contrast, claims 1 and 29 of the '213 patent fully describe the concept of testing within step B: the claim preamble is merely extolling the virtues of the patent and, according to SynTest, is not necessary to provide structure to the claim.23 Similarly, the preamble from claim 1 of the '323 patent is not limiting, according to SynTest, because the purported limitation that N be greater than one is fully described in step B of claim 1.

Cisco disagrees, relying upon the Federal Circuit teaching that when "limitations in the body of the claim rely upon and derive antecedent basis from the preamble, then the preamble may act as a necessary component of the claimed invention."24 According to Cisco, because all three preambles here supply antecedent bases for limitations that follow, all three claim preambles are limiting.

SynTest has the better of the argument, at least on the merits. The determination of whether preambles are limiting necessarily affects the meaning — and therefore the size and scope — of the asserted claims.25 Absent guidance on whether the preambles limit the scope of asserted claims, the jury would be invited "to choose between alternative meanings" of the disputed claims generating O2 Micro error. This court thus must resolve this "actual dispute regarding the proper scope" of the claims.26 Because the body of claims 1 and 29 of the '123 patent as well as claim 1 of the '323 patent "describe a structurally complete invention,"27 the preambles to those claims do not limit the meaning of the claims. A careful review shows the disputed language in the preambles as to those claims is repeated in the body of the claim and Cisco identifies no instance in which these preambles provide a unique description of structure referenced later in the claims. In short, there are no necessary antecedent bases in these preambles. In contrast, because the preamble to claim 1 of the '126 patent is necessary for limitations A through E to have meaning, that preamble is limiting.

B. Dispute #2: "Providing Ordered Capture Clocks"

Two disputes lie between the parties over the construction of "providing ordered capture clocks": (1) whether triggering should be incorporated into the construction and (2) whether a capture clock should be defined as a test clock.

1. Triggering Should Be Incorporated Into the Construction

The asserted patents specifically describe the "invention"28 as using either "daisy-chain clock triggering" or "token-ring clock enabling" techniques for providing or applying ordered capture clocks:

Both techniques require generation of capture clock pulses for one clock domain in direct response to a capture clock pulse in another clock domain. For example, in the daisy-chain technique, the occurrence of a transition (e.g., from low-to-high or high-to-low) of a preceding clock domain's capture clock pulse triggers generation of capture clock pulses in the next clock domain.31 The token-ring technique is similar, except that the next domain's capture clock pulses are activated based on the occurrence of a particular signal level (e.g. low or high) in the preceding domain's capture clock pulses.32 In other words, daisy-chain clock-triggering "uses clock edges to trigger the next operation" and token-ring clock-enabling "uses signal levels to enable the next operation."33 For both options, the occurrence of the first capture clock pulse of one of the clock domains depends directly on the activity of a capture clock pulse of a previous clock domain.

The term "triggering" encompasses the response requirement because the applicants specifically used the term "triggered" to describe how the claimed invention provided ordered capture clocks in both the '126 and '323 patents.34 The term also is consistent with the applicants' generic use of the term "trigger" during prosecution of the '213 patent when discussing how the Nadeau-Dostie2 reference "triggered" its domains.35

Because the patentee relied on the claim requirement of "applying an ordered sequence of capture clock pulses" in "a sequential order" during prosecution to distinguish the prior art,36 use of the trigger term is appropriate in the court's construction. At bottom, the foundation of the asserted patents is that the test in the second domain is triggered based on the completion of the test in the first domain — once the first domain is done, the second domain then is activated.37

2. A "Capture Clock" Should Not Be Limited to a "Test Clock"

The term "capture clock" appears multiple times in each asserted claim of each asserted patent. The parties generally agree that the term "capture clock" in the asserted patents means a "reconfigured system clock."38 This construction is consistent with language from the asserted patents that the "reconfigured system clocks are called capture clocks."39 The parties also agree that a single construction ought to control the same term's meaning across the family of patents.40

Despite this agreement, SynTest urges that the court substitute the term "capture clock" with the generic term "test clock." SynTest points to the patentees' use of "test clock" once during the prosecution history when referring to the capture clock. But this does not justify SynTest's proposed substitution.41 When the patentees used the "test clock" term they were merely pointing out that the capture clock in these claims was being used to perform testing and that this particular capture clock was a special type of clock: a clock that provided both capture clock pulses and shift clock pulses, depending on the mode of operation:

While it is therefore true that the capture clock claimed in the asserted patents can be used during testing, it does not follow that every "test clock" is a capture clock as claimed in the asserted patents. Indeed, not every test clock is a "reconfigured system clock," which the parties have agreed and the patents confirm is the claimed "capture clock." And not every test clock is the special type that contains both capture clock pulses and shift clock pulses depending on the operational mode — as the patentees stressed the claimed "capture clock" was in this case.

The other justification for using the term "test clock" in this construction is the unremarkable observation that "external tests, like ATEs, are applicable to the present" invention42 combined with a statement from the specification that, when "scan test is employed, the multiple-capture DFT system is usually resided in [sic] an ATE and, thus, all capture clocks are controlled externally."43 There is no dispute, however, the reconfigured system clocks that are the "capture clocks" in the asserted patents can be generated internally or controlled externally. The patents explain that the system clocks can be generated inside of the circuit being tested or can be received from an external source at one of their input pins.44 Whether generated internally or controlled externally, the capture clocks are reconfigured system clocks, and they are clocks that contain both shift clock pulses and capture clock pulses, depending on the operational mode.

In sum, construing the term capture clock to be a test clock is not warranted.

C. Dispute #3: "Applying an Ordered Sequence of Capture Clock Pulses to All Said Scan Cells Within Said N Clock Domains in Said Normal Mode During a Capture Operation, the Ordered Sequence of Capture Clock Pulses Comprising at Least Two Capture Clock Pulses From Two or More Selected Capture Clocks, for Controlling Two or More Clock Domains, in a Sequential Order"

Here, the parties dispute (1) whether "applying an ordered sequence" should be limited to "triggering" (2) whether the capture clock pulses must come from the capture clocks and (3) whether the pulses must be applied to each of N clock domains and (4) whether the phrase "without including shift clock pulses in the capture window" should be included.

In light of the central nature of the triggering concept to the asserted patents discussed above, triggering is included in the court's construction.

SynTest's proposed construction removes the requirement that "capture clock pulses" come "from two or more selected capture" clocks45 and instead permits the capture clock pulses to come from anywhere. Its proposed construction also eliminates the requirement that the "ordered sequence of capture clock pulses" must be applied to "all scan cells within each of N clock domains of the integrated circuit or circuit assembly during a capture" operation46 and refers to "continuing with this sequential order until the test is complete," an indefinite concept. Such a construction would provide an argument that a test is "complete," even where (1) capture clock pulses have not been applied to all scan cells within each of N clock domains (2) during a capture operation — features explicitly recited in the claim. These modifications are not warranted.

Cisco also urges the construction also inappropriately reintroduces claim limitations that the applicants deleted from the claims during prosecution in response to a claim rejection.47 During prosecution of the '213 patent, the PTO specifically objected to the claim phase: "and does not contain any said shift clock pulse during a capture operation" as being not enabled. Patentees responded by deleting that phrase from the claims.48 A construction that reads that limitation back into the claims is not warranted.49

But inspection of the prosecution history reveals such a narrow view of the claim language is not warranted. It is correct that, in response to the Examiner's Section 112 objection, the applicants deleted language from the claim and agreed with the Examiner's statement that only capture clock pulses can occur during the capture cycle, when the scan enable signal is inactive.50 As pointed out to the Examiner during an interview with Dr. Wang and as demonstrated in the diagram Dr. Wang provided, however, the prior art recognizes a distinction between the capture cycle and the capture window or capture operation for purposes of fault testing.51 Specifically, the prior art LOS methods for delay fault testing require that a last shift clock pulse launch the capture operation.52 This distinction with the prior art is reflected in the specification.53 Cisco failed to satisfy its burden of proof that SynTest "unequivocally disavowed a certain meaning to obtain his patent."54

D. Dispute #4: "Applying an Ordered Sequence of Capture Clocks to All Said Scan Cells Within Said N Clock Domains, the Ordered Sequence of Capture Clocks Comprising at Least a Plurality of Capture Clock Pulses From Two or More Selected Capture Clocks Placed in a Sequential Order Such that All Clock Domains Are Never Triggered Simultaneously During a Capture Operation"

In addition to the disputes resolved in the two preceding constructions, dispute number four raises the additional issues of whether the construction should (1) delete "during a capture operation" from the claim — to prohibit simultaneous triggering even during the shift operation, (2) whether the term "activated" can be substituted for the term "triggered," (3) whether one capture clock may control multiple clock domains and (4) whether the agreed construction of "capture clock" can be substituted with "test clock from which is derived a system clock."

This claim term is similar to the claim phrase reviewed above, except that it contains an additional requirement that "all clock domains are never triggered simultaneously during a capture operation." The court will not rehash its analysis above.

SynTests's construction of this term also deletes "during a capture operation" from the claim phrase "such that all clock domains are never triggered simultaneously during a capture operation." Although the claim specifically states the time period when all clock domains should not be simultaneously triggered — during a capture operation — the proposed construction removes that language from the claim so that the claims also prohibit simultaneously triggering clock domains during a shift operation. This construction that is inconsistent with the relevant specifications. For example, Figure 13 of the '323 patent illustrates that the first pulses in the shift cycle for all clocks are triggered simultaneously. The proposed construction transparently and retroactively sidesteps prior art: this is improper.

Without justification SynTest's proposed construction also substitutes the term "activated" for "triggered." Elsewhere in its argument, SynTest draws a distinction between "triggering" and other types of activation (e.g., enabling), but no accounting of the difference between the two is laid out in support of such a distinction. If "triggered" only referred to the very specific "daisy-chain" technique, it would be inappropriate to substitute the specific term "triggered" with a generic term "activated." Because the claim uses the term "triggered," the same term should be used in the construction.

E. Dispute #5: Independent Claims 1 and 29 Do Not Require Delay Fault Testing to Be At Speed

Cisco urges the delay fault testing must be done at speed, but SynTest counters this construction is inconsistent with dependent claim 15 that claims delay fault testing at speed. If at speed is read into the independent claims 1 and 29 and then dependent claim 15 is rendered a nullity under the doctrine of claim differentiation.55

The court agrees with SynTest. "The doctrine of claim differentiation is `based on the common sense notion that different words or phrases used in separate claims are presumed to indicate that the claims have different meanings and scope.'"56 "The doctrine is not a hard and fast rule, but instead "a rule of thumb that does not trump the clear import of the specification.'"57 In this case, a common sense comparison of the independent and dependent claims shows that the additional requirement of default testing at speed should not be read into the claim.

F. Dispute #6: The Ordering of Claim Steps 1(a) Through 1(e) of Claim 1 of the '126 Patent

Claim 1 of the '126 patent provides for certain steps in a particular order:

The parties dispute whether the method claim elements listed above must be performed in order.59 SynTest urges that for the order of a method claim to be binding it must be "unequivocally dictated;"60 but Baldwin Graphics does not support such a per se requirement. The Baldwin court's holding was milder: the claim need only "implicitly or explicitly" require a specific order in light of the specification.61 Here, all of the multiple-capture rule violations must be identified before steps (d) and (e) may be completed. It is insufficient for any violation to be missed, because the resulting netlist then may not detect the faults in design. The court holds — and the parties agreed at oral argument — that not all violations must be identified before each may be fixed — step B need not be completed, in its entirety, before Step C is performed.

G. Dispute #7: The Meaning of Checking Whether Said Design Database Contains Any Multiple Capture Violations

In the design of an ASIC, the goal is to fix all rule violations. The parties dispute whether the claim requires all rule violations to be identified before all identified rule violations can be fixed. The dispute with respect to whether such an ordering is required turns on whether "`any' multiple-capture rule violation as used in the Claim step 1(b) refers to `all' multiple capture violations."62 If after a review, no multiple-capture rule violations are found, the next step of fixing all rule violations is completed by doing nothing. Similarly, Cisco's reference to the use of the word "any" in the specification as it relates to clock skews is simply unavailing. The term "any" is used repeatedly in the claim language itself, without signifying all is meant. For example, the preamble states that what is claimed is an "apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains."63 Any cannot mean all in this context. Similarly, one dependent claim includes the phrase "applying said capture clock pulses concurrently to two or more selected clock domains which do not interact with each other or do not have any logic block crossing."64 Any could not mean all in this context, either.

The parties agree that multiple-capture refers to a method for delay testing.65 Cisco does not contend that there is anything indefinite about the term "rule violations" as it relates to delay fault testing of an ASIC in design. One "of ordinary skill in the relevant art could not discern" that multiple-capture rules violations refer to delay testing violations that would apply to the multiple-capture methods of delay fault testing.66

H. Dispute #8: "Each Shift Clock Pulse Comprising a Clock Pulse Applied in Scan Mode"

The parties agree that "each shift clock pulse comprising a clock pulse applied in scan mode" can be construed as a pulse of a test clock when scan enable is active. Cisco attempts to limit the clock that can generate this pulse to a reconfigured system clock, the same clock generating the capture clock pulses with both the shift clock pulses and the capture clock pulses being generated at the same frequency. This construction ignores the specification, which identifies the reach of the invention to embrace both self-test and scan-test.67 Additionally, the specification recognizes that separate clocks can be responsible for shift clock pulses and capture clock pulses.68 As Cisco acknowledges, while adequate delay fault testing requires capture clock pulses be at-speed69 "the shifting frequency is irrelevant to at-speed testing."70 This is because "testing of delay faults at-speed [with this invention] is now performed by applying two consecutive capture clock pulses (double captures) rather than using the shift followed-by-capture clock pulses."71

I. Dispute #9: "Each Capture Clock Pulse Comprising a Clock Pulse Applied in Normal Mode"

The discussion to dispute number eight applies with equal force to dispute number nine.

J. What Means-Plus-Function Structures are Disclosed in the Specification of the '323 Patent

Because the parties agree on the function, the only issue before the court is the corresponding structure. The parties agree that there are two elements to the structure: (1) generating N test stimuli and (2) shifting in N test stimuli to all said scan cells. With respect to the first structure, Cisco contends that "the specification unambiguously explains that PRPGs combined with phase shifters are used to generate test stimuli."72 Cisco ignores that the phase shifters are identified as "optional" by the patent.73 Moreover, by citing only to the PRPG, Cisco again attempts to limit the invention to self-test. A PRPG is not a requirement for scan-test.

Cisco identifies the "capture clock" as the structure for the second element citing that "[d]uring each shift cycle" a "series of pulses" are "applied through capture clocks" to shift stimuli to all scan cells within all clock" domains.74 Cisco again cites to the capture clock in an effort to read out scan-test, which is inappropriate for all the reasons discussed above.

By contrast, and to address the fact that the invention covers both scan-test and self-test, SynTest identified the DFT system as the structure for both the generation of test stimuli and the shifting in of data. The specification explicitly supports this structure as performing both functions in both scan-test and self-test.75 SynTest argues that the shifting operation is different from the capture operation and the clocks therefore need not be at the same speeds and can originate from different clocks. Cisco's construction improperly requires a scan-enabled system, but the claim language does not require this limitation.

The court agrees that scan design is not completely dependent upon the use of a scan-enabled signal. While the use of a scan-enabled signal may be the most common way to shift data in and out of a scan chain during test, the specification makes clear that the "multiple-capture DFT system of the present invention further comprises any method or apparatus for performing the shift operation at any selected clock speed within each clock" domain.76 The specification also recognizes that separate clocks can generate shift clock pulses and capture clock pulses.77 Cisco's additional limitations are unwarranted.

IT IS SO ORDERED.