DONAVAN W. FRANK, District Judge.
This matter came before the Court for a pre-trial hearing on September 3, 2014. It is the Court's intent, as suggested during the hearing, that this case will be tried in substantially the same manner and with the same rulings as the first and second trial, with the exception with respect to the first trial that the Court will follow the mandate of the Eighth Circuit with respect to the jury instruction that defined the phrase "knowingly false representation." (Doc. No. 254.)
Consistent with and in addition to the Court's rulings and remarks from the bench, and based upon the memoranda, pleadings, and arguments of counsel, and the Court having reviewed the contents of the file in this matter and being otherwise duly advised in the premises, the Court hereby enters the following:
1. Plaintiff's Motion to Exclude Evidence Regarding Employment Opportunities that are Not Substantially Equivalent (Doc. No. [458]) is
2. Plaintiff's Motion to Exclude Certain Expert Testimony from Dr. Mark Meitzen (Doc. No. [460]) is
3. Plaintiffs' Motion to Exclude Defendants' Trial Exhibits (Doc. No. [462]) is
4. Plaintiff's motion to have the jury decide his legal claim of promissory estoppel (Doc. No. [466]) is
5. Plaintiff's motion to reinstate the Court's previous judgment entered December 10, 2010 (Doc. No. [469]) is
6. Plaintiff's motion to overrule Defendant's objections to subpoena duces tecum (Doc. No. [473]) is respectfully
7. Defendants' Motion to Exclude the Testimony of Roger Rolbiecki (Doc. No. [422]) is
8. Defendants' Motion to Exclude References to Prior Verdict or Outcome (Doc. No. [426]) is
9. Defendant's Motion to Preclude Plaintiff's Promissory Estoppel and Front Pay Claims from Submission to the Jury (Doc. No. [429]) is
10. Defendants' Motion to Exclude Evidence, Testimony, and Instructions Regarding Disputes Over the Re-imaging of Plaintiff's Laptop (Doc. No. [445]) is
11. Defendants' Motion to Exclude the Expert Report and Testimony of Barry Crawford (Doc. No. [437]) is
12. Defendants' Motion to Exclude the Expert Report and Testimony of James Jensen (Doc. No. [441]) is
13. Defendants' Motion for Sanctions (Doc. No. [454]) is
MR. BRENT SNYDER: Just one witness, Your Honor, the Plaintiff calls Roger Rolbiecki.
THE COURT: Sir, if you want to step to the front of the courtroom? The witness stand is over here. Once I get you close to the front, I will administer the oath. If you would please raise your right hand?
(Witness sworn.)
Then there is a step up there, sir. If you want to have a seat behind the microphone and then once you move up to the microphone, if you would please state your full name and spell your last name?
THE WITNESS: Roger Rolbiecki,
R-o-l-b-i-e-c-k-i.
THE COURT: You may inquire whenever you are ready, Counsel.
BY MR. BRENT SNYDER:
Q. Good afternoon. Thank you for being with us this afternoon, Mr. Rolbiecki. I understand that you are here pursuant to subpoena, is that "correct?
A. That is correct.
Q. Please give us a — please tell us your educational background.
A. I have undergraduate degrees in math and physics, and a Master's Degree in Physics.
Q. From what University?
A. From Winona State University and Ohio University in Athens, Ohio, on the Master's.
Q. What year was your Master's Degree?
A. In 1978.
Q. Can you give me a brief overview of your professional experience since 1978?
A. I have been employed in the semiconductor industry since 1978 and I have worked primarily in the semiconductor industry performing device analysis, yield enhancement, physical design, design support, software' support, design tools.
Q. Which organizations have you worked for?
A. I have worked for yield enhancement at DTC Semiconductor; Fairchild Semiconductor, Cypress Semiconductor, AMI Semiconductor.' I have also worked at Control Data as' a consultant, at Sperry Univac as a yield enhancement engineer, SLE as a design engineer, CAD engineer, worked at Seagate as a design engineer, and also in Guidant as a physical design engineer in the medical industry.
Q. When — well, I should ask this. What, is your current vocation?
A. I am currently self-employed, working under my own LLC company, Go Semis. And I am performing engineering support to the industry.
Q. And what is your hourly rate?
A. It is at $115 an hour.
Q. And I believe the Plaintiff is compensating you for your time away from your business?
A. Yes, that is correct.
Q. Tell me when you began working for Seagate?
A. I began April, the end of April of 2007.
Q. What position were you hired to at that time?
A. I was hired to do PDK development that is Process Design Kit development to support the design of magnetic memories.
Q. Were you ever a member of the ATG crew?
A. Yes, I was.
Q. When did you become a member of that group?
A. Well, ATG was the group that we were hired into. It was both design and process.
Q. And that was 2007?
A. 2007, April of 2007.
Q. Do you know the Plaintiff in this case, Dr. Vaidyanathan?
A. Yes, I do.
Q. How do you know him?
A. Through work at Seagate.
Q. Do you remember when you first met him?
A. Roughly the end of 2007, you know.
Q. Was it after he was already an employee at Seagate?
A. Yes.
Q. Were you involved in his hiring at all?
A. No, I had no involvement at all.
Q. Or his recruitment? Did you have any involvement in his recruitment and or hiring?
A. No, I had no knowledge of the hiring process, recruitment or hiring process.
Q. Did you know him at all while he was employed with Texas Instruments?
A. No, I did not.
Q. Did you understand he was a yield engineer at Texas Instruments?
A. Yes, I did.
Q. What was your understanding that he was hired to do at Seagate?
A. I understood that he was a yield enhancement engineer.
Q. Did Seagate employ any other yield enhancement engineers within that ATG group?
A. Not to my knowledge.
Q. Please describe for me the interaction you had with him while you were both employed within the ATG?
A. Well, we were all primarily working on the future generation of the memory bit cell, and the design rules. So, the entire organization was involved in revising the process or revising the design rules, revising the next generation memory cell.
Q. Working on a product, if you will?
A. Working on test chips, and also potentially a higher density in memory array.
Q. What was the status of those test chips during this 2008 time period?
A. They were fluid. They were in constant revision. They were being designed and enhanced along the way as more knowledge became available to us, and also as new semiconductor processing became available to us.
Q. Was there a baseline in place?
A. There was not a baseline.
Q. Was there a repeatable process?
A. There was not a repeatable process.
Q. Your experience as a yield enhancement engineer at prior organizations, how many years did you spend performing those duties for organizations?
A. I would say easily six.
Q. Can you give me an idea of what those duties were that you performed in that function?
A. Well, at Cypress Semiconductor, they were a memory house. They produced SRAMs, which is different from an MRAM. We performed parateo analysis, bitmapping, trend charting, process flow, you know, statistical process flow of data versus, you know, in-line data, final test data versus in-line test data.
At Fairchild Semiconductor, it was a large logic house. You know, our duties there were based on a statistical analysis of a process that is running, it was based on a process they had and established yield. The duties were to sustain existing yields, and also through enhanced yields, by again using statistics.
Q. At those organizations, tell me about the status of the product that you were working on?
A. Well, there was always in existence to do yield enhancement, there was always an existing baseline to characterize your process from. It was then possible to enhance the yield.
It was a division between, you know, a mature process that you could do enhancement on, versus a process that was under development.
Q. I am going to put exhibit, Plaintiff's Exhibit 6 back up here. And Plaintiff's Exhibit 6 has the title, yield engineer position.
Did you perform any of these functions in your previous roles as a yield engineer?
A. Yes, I have.
Q. Which ones?
A. Bitmap analysis, run correlations between in-line fab data and electrical data to identify signals for product yield improvements, correlate wafer bin fallout, layer defect in-line and be able to perform statistical analysis, work with the failure analysis groups to determine the root cause of the failures.
The candidate must be able to engage in tool vendors for testing. I did not do that. There was a specific group that would normally service the testing functions.
Candidate must have a strong cross-functional understanding of device and process, that is true.
Q. Did you perform any of these functions while you were employed in the ATG group?
A. No, I didn't.
Q. You weren't a yield engineer there, were you?
A. No, I was not.
Q. Please describe for me your interaction with Dr. Vaidyanathan, whether monthly, weekly, daily, if you can describe that for us, please.
A. Well, certainly. It was, you know, multiple times a week. It was not necessarily daily, but we were all closely tied together in developing next generation process and next generation, you know, memory and test chip. So, we would interface quite regularly between the design groups and the process groups. It was on a one-to-one basis, it was on a group basis. We only held, you know, we had strong communication meetings that, you know, there was a technical exchange on a regular basis that people were invited to discuss what they are working on for information exchange and also to educate, you know, former co-workers.
Q. Did you have an opportunity to observe Dr. Vaidyanathan at work?
A. Yes.
Q. When you were observing him at work, did you see him performing any of these functions as stated? I will take them one by one.
First one, bitmap analysis to generate yield parateo, et cetera. Did you see him perform those functions?
A. No, I did not see him perform that.
Q. How about number two?
A. I did not see him perform that.
Q. How about number two?
A. I did not see him perform that, either. Three?
A. I did not see number three.
Q. How about four?
A. No, I did not see four.
Q. How about the others?
A. I did not see the engagement with tool vendors. I believe that the candidate has a strong cross-functional understanding of process and device. believe that was indeed true.
Q. True for you, as well, probably?
A. Yes, and many of the others—
Q. And for most of the other members on the team.
A. Um, the candidate must be able to lead cross-functional teams, I believe that was true; and coordinate, certainly coordinate activities with design process product and reliability engineering, was true.
Q. I want to focus on these top four for the next couple of questions. Are these duties consistent with your understanding of a yield enhancement engineer?
A. Yes, they would be.
Q. Did you see anybody at Seagate performing these functions?
A. It would be possible to do this for an experimental basis, but to statistically do yield enhancement by using bitmap analysis and trying to correlate in-line data to electrical data, if there is not any baseline yield, is a task that cannot be done.
Q. Are you employed at Seagate any longer?
A. No, I am not.
Q. When did you, when did your employment with Seagate in the ATG end?
A. My employment ended May 13th of 2009.
Q. Was that a part of a reduction in force?
A. Yes. The entire organization was reduced.
Q. I want to talk to you about the status of the ATG in 2007. This would have been your first year, I believe. That you were employed within the ATG.
A. That is correct.
Q. And I think you said April is when you started?
A. The end of April, yes.
Q. Now, what did — what did you hear during that time at meetings and the like about the status of the ATG? Where was it?
A. It was my understanding that Seagate had some aggressive goals, that we were all involved with development of initial memory cell to improve the technology. And we also were exercising the design functions, we were exercising the process functions, you know, we had aggressive goals to release a chip as soon as possible to evaluate the memory of the bit cell.
Q. What did you hear about the future of the organization?
A. You know, initially, there was a very aggressive posture and it seemed to have total support of Seagate behind our activities. We produced a test chip, and after the test chip was processed and came out of fab, there seemed to be a slight change in the direction. And the initial bit size of the device that came out was large. And that meant that the device was not suitable for our production device. You have to have a certain density in a memory array to be competitive with other technologies.
So, there was some constraints in the bit cell design that limited the usefulness of the device for production. And the fact that it did not yield when it came out, it constrained the ability to characterize the process.
Q. What did Seagate want to do about this?
A. Well, I think that it was the realization that more aggressive semiconductor technology had to be obtained that, you know, it could be obtained either through partnership, through merging, through the-sale of the ATG.
You know, I think that the hopes of the organization, you know, were to continue with the memory, the magnetic memory. I believe it was certainly' my feeling and many others that the solid state memory was the direction that Seagate needed to pursue.
And at some point, you know, when the bit cell was too large and the yields were not there, you know, it was my understanding that another strategy had to be obtained, besides having Seagate solely funded, you know, the solid state memory had to be produced in volume. If it was a competitive technology with Seagate having $13 billion in revenue, they produced quite a few disk drives. So, you would have to have a pretty major effort into the development of a magnetic, you know, memory.
A. It was my perception that the process portion of ATG continued to grow at higher rate than the design. And it was my belief that this would be consistent with establishing the appearance of having a credible semiconductor facility. And a credible semiconductor facility would have a baseline yield, would have a baseline process, would have an organization that supported that function. And if the company would be sold, it would be beneficial to have an all inclusive function as a stand-alone semiconductor house, even though we didn't have all of the process tools that we needed.
It would make it — the emphasis was in structure of ATG, the emphasis was on developing intellectual properties which, you know, gave us value as a stand-alone company, just the memory portion of it. Those are my perceptions of the things that had changed.
MR. BRENT SNYDER: I don't have anymore questions at this time.
THE COURT: You may inquire if you wish.
BY MS. ROBBINS:
Q. Hi, Mr. Rolbiecki. How are you this afternoon?
A. Fine.
Q. Good. I have a few questions for you. First of all, did you work with good people at the ATG?
A. Yes, of course.
Q. Smart people, capable people?
A. Yes, very capable.
Q. And really across the board there were 100 some people at one point smart, capable people; correct?
A. Yes, very capable.
Q. A lot of people with Ph.D.'s?
A. Yes.
Q. A lot of people with deep backgrounds like your many years of experience?
A. Yes.
Q. And would you agree that it was an interesting, challenging project?
A. Yes, it was.
Q. Did you go there to the ATG because you found it to be an interesting project?
A. No.
Q. That didn't — it didn't interest you when you moved there?
A. You know, I had another interesting project there I was working on.
Q. And you testified about having some years of experience. And did you — when did you work in the yield area?
A. You know, 1980 through 1992, roughly.
Q. I thought you had testified that you worked about 6 years in yield engineering.
A. I did. You know, not all of those years were exclusively yield engineering, yield enhancement, so I tried to segregate it to exactly when I was performing those duties.
Q. I understand. So, you worked in yield engineering on and off between 1980 and 1992?
A. Yes. You know, it was a shared responsibility that sometimes it was exclusively yield enhancement, and sometimes I would migrate into different duties.
Q. Okay. So, you would go into different areas, but you could still come back to doing yield engineering at another time?
A. It wasn't that, you know, fluid. You did yield enhancement and then you left and you did a different job.
Q. Okay, and then you came back and did more yield enhancement?
A. Not in all cases, no. Sometimes it was a permanent switch. And in the later years it was kind of a permanent switch.
Q. So, sometimes it was consistent, sometimes it was on and off?
A. Right.
Q. All right. And we have heard some testimony that yield engineering changes very rapidly, is that true?
A. Can you elaborate on the question a little bit more about the change, what changes.
Q. Did the skills you need for yield engineering change very quickly?
A. Well, I wouldn't say so, you know, there is a core set of skills, you know, being able to understand a process. And if you certainly change the process, you change your skills and learn a new understanding, you know, but the techniques employed, parateo analysis, trend charting, statistical analysis, those are all pretty standard in the industry.
Q. So, is it your testimony that if you are in yield engineering at one time, you could get back into it at a later date without much trouble?
A. Well, no, the — you know, going back into yield engineering requires the understanding of the process. It understands, you know, obviously somebody would have to hire you. And you know, that is one thing that I offer as far as consulting, but I have not had anybody that took me up on yield enhancements.
Q. So, you do yield consulting, even though you haven't actually worked in that field since 1992?
A. It is something I put on my resume, you know, as a skill set. You know, whether I can do that, I have not been able to do that again. You know, traditionally, what the industry looks at, you know, is your last job. I would have a much higher probability getting into the design, you know, PDK development that I was doing at Seagate, rather than going back on an old skill set.
Q. Given that you have it on your resume, do you think you would be capable of continuing to do some yield engineering?
A. I think, certainly, everybody is retrainable. You can relearn skills. What I have observed in the industry is that the long-term vision of companies is no longer there. You know, people don't want to retrain you. They don't want to invest in an employee over the long-term, they want somebody that can come in, perform a certain function, which is why I am trying the consulting fee, because you go in and you have an opportunity to work a month, or two months or three months, and then you are done.
Q. Okay. But, during that period in 1980 through 1992, you did yield engineering on that on-and-off basis as we discussed, right?
A. Yes.
Q. You are here today as a paid witness, is that correct?
A. That is correct.
Q. And your rate, did you say — what did you say your rate was?
A. It was $115 an hour.
Q. And so did you charge also for time that you worked with Plaintiff's — with Dr. Vaidyanathan's lawyers?
A. Yes.
Q. How much time have you charged Dr. Vaidyanathan for this case?
A. It would be four hours.
Q. And with respect to Dr. Vaidyanathan, is he someone that you were friendly with when you worked at Seagate?
A. Yes, I hope I was friendly with everyone. Have you remained in touch with him since he left Seagate?
A. No, unfortunately not.
Q. You mentioned that when you were working at Seagate, all of the people who were working in the ATG were, I think the phrase you used was closely tied? And I am getting the sense that that is closely tied within the work that they did, is that right? 4
A. Yes.
Q. That whole group of the ATG, right?
A. Yes.
Q. And that would include Christina Hutchinson?
A. Yes. Not as closely, you know, because her functions and'mine didn't overlap; but, certainly, you know, we all had regular meetings together.
Q. Would that include Andrew Habermas?
A. Yes. Oh, Andrew, yes, for sure.
Q. Would that include Sriram Viswanathan? No.
Q. He was in the ATG, right?
A. I don't remember the name.
Q. You don't remember — okay. That is fair enough. One of the things you mentioned was the word, the baseline. What do you mean by baseline?
A. Baseline is the validation of a process. And that is"through a yield. And when you have — you have to have some product that you run to characterize your fab. And when you run the product, it establishes a baseline. A baseline is a given yield, it helps you characterize, you know, the defect density of the fab, it gives you kind of a signature of this state of how your fab is running. And from a baseline, you can infer what a different style product will do.
Say if you have a memory device, typically they run a small memory device, establish a baseline yield, you know, do bitmapping of that device to establish a defect density. You can infer, then, you know, what will happen on a larger chip or potentially on a different type of chip. It could be a logic chip versus a memory chip.
Q. And you had two test chips by the fall of 2007 in the ATG, correct?
A. Yes.
Q. With respect to yield development, which is the way you described some of your past experience, is the idea of yield development to move to higher yield?
A. Yes.
Q. You want the yield to get better, right?
A. Yes, that is true.
Q. So, if there
A. That is not a baseline enhancement, it's a —
Q. That is not the question I asked.
A. Oh, I'm sorry.
Q. I just asked you if you want to get — from O, you want to get to 1. If you get to 95, you"want to get to 100?
You testified that the yields weren't there. So there was something called a yield, correct?
A. O yield.
Q. So, you are saying there was absolutely no yield of what?
A. There was never a die that functioned at 100 percent.
Q. Were there bits working on a chip?
A. I am sure there were, yes.
Q. And were there bits working on some chips at high yield?
A. You know, I am sure the yield varied, you know. I would not say high yield.
Q. Okay. But, you weren't a yield engineer at Seagate, right?
A. No.
Q. So that wasn't your job to find that out, right?
A. No, it was not.
Q. And you didn't do failure analysis, correct? No. I did not.
Q. You weren't in the test group?
A. I was not.
Q. To whom did you report?
A. I reported into Harry'Liu.
Q. So, not to Antoine Khoueir, right?
A. No, I did not.
Q. So, you were in a different reporting structure than Dr. Vaidyanathan, correct?
A. That is correct.
Q. And then you would all report up to Brian Lee, or not?
A. No, Harry Liu was parallel to Brian Lee.
Q. So, Dr. Vaidyanathan reported to Antoine Khoueir, right?
A. Yes, that is right.
Q. And Mr. Khoueir reported to Brian Lee, correct?
A. That is correct.
Q. And Mr. Lee reported to Mr. Ryan, correct?
A. That is correct.
Q. And so you reported to Mr. Liu, correct?
A. Harry Liu.
Q. Harry Liu. And Harry Liu reported also to Mr. Ryan, is that —
A. Initially, that is true, but if my memory is correct, at some point Harry Liu reported in to Brian Lee. It didn't really matter, because that was another level beyond.
Q. Was there some fluidity in terms of people were working in different groups with one another?
A. Everybody was working together.
Q. Okay. You looked at that list of job duties with the bullet points on it, and you testified that the last four bullet points, you saw Dr. Vaidyanathan do all of those things, correct?
A. Yes, that is correct.
Q. Would it also be correct that you did not observe everything he did?
A. That is true, yes.
Q. You weren't his boss?
A. No, I was not.
Q. And you didn't follow him around?
A. No, I did not.
Q. You had other things to do, right?
A. Yes, that is correct.
Q. And you never interviewed Dr. Vaidyanathan, correct?
A. I did not interview him.
Q. You did not sit in on any interviews with him?
A. No, did not.
Q. You never talked to him during the recruiting process, right?
A. I did not.
Q. You never knew what was said to him during that process?
A. That is correct.
Q. And was your employment terminated by Seagate?
A. Yes, it was.
Q. When did that happen?
A. It was May 13th of 2009.
MS. ROBBINS: I have no further questions. Thank you Mr. Rolbiecki.
BY MR. BRENT SNYDER:
Q. Just one quick follow-up. Mr. Rolbiecki, I think you mentioned a moment ago there was never a functional die in the ATG group?
A. Yes that is true.
Q. Tell me why that is significant in terms of yield enhancement engineering?
A. That establishes your baseline. In order to do bitmap analysis and characterize your fab, that you need a functional die enabled to establish a defect density. You need some working device, you know, that works' 100 percent to do yield enhancement.
MR. BRENT SNYDER: Okay. No more questions.
MS. ROBBINS: Nothing further, Your Honor.
