CLAIM CONSTRUCTION ORDER

SUSAN ILLSTON, District Judge.

On May 23, 2012, the Court held a claim construction hearing. After consideration of the parties' papers and presentations, the Court construes the claims at issue.

LEGAL STANDARD

Claim construction is a matter of law. Markman v. Westview Instr., Inc., 517 U.S. 370, 372 (1996). Terms contained in claims are "generally given their ordinary and customary meaning." Phillips v. AWH Corp., 415 F.3d 1303, 1312 (Fed. Cir. 2005). "[T]he ordinary and customary meaning of a claim term is the meaning that the term would have to a person of ordinary skill in the art in question at the time of the invention." Id. at 1312. In determining the proper construction of a claim, a court begins with the intrinsic evidence of record, consisting of the claim language, the patent specification, and, if in evidence, the prosecution history. Id. at 1313; see also Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996). "The appropriate starting point . . . is always with the language of the asserted claim itself." Comark Communications, Inc. v. Harris Corp., 156 F.3d 1182, 1186 (Fed. Cir. 1998); see also Abtox, Inc. v. Exitron Corp., 122 F.3d 1019, 1023 (Fed. Cir. 1997).

Accordingly, although claims speak to those skilled in the art, in construing a claim, claim terms are given their ordinary and accustomed meaning unless examination of the specification, prosecution history, and other claims indicates that the inventor intended otherwise. See Electro Medical Systems, S.A. v. Cooper Life Sciences, Inc., 34 F.3d 1048, 1053 (Fed. Cir. 1994). The written description can provide guidance as to the meaning of the claims, thereby dictating the manner in which the claims are to be construed, even if the guidance is not provided in explicit definitional format. SciMed Life Systems, Inc. v. Advanced Cardiovascular Systems, Inc., 242 F.3d 1337, 1344 (Fed. Cir. 2001). In other words, the specification may define claim terms "by implication" such that the meaning may be "found in or ascertained by a reading of the patent documents." Vitronics, 90 F.3d at 1584 n.6.

The claims must be read in view of the specification. Markman, 52 F.3d at 978. Although claims are interpreted in light of the specification, this "does not mean that everything expressed in the specification must be read into all the claims." Raytheon Co. v. Roper Corp., 724 F.2d 951, 957 (Fed. Cir. 1983). For instance, limitations from a preferred embodiment described in the specification generally should not be read into the claim language. See Comark, 156 F.3d at 1187. However, it is a fundamental rule that "claims must be construed so as to be consistent with the specification." Phillips, 415 F.3d at 1316. Therefore, if the specification reveals an intentional disclaimer or disavowal of claim scope, the claims must be read consistent with that limitation. Id.

Finally, the Court may consider the prosecution history of the patent, if in evidence. The prosecution history limits the interpretation of claim terms so as to exclude any interpretation that was disclaimed during prosecution. See Southwall Technologies, Inc. v. Cardinal IG Co., 54 F.3d 1570, 1576 (Fed. Cir. 1995). In most situations, analysis of this intrinsic evidence alone will resolve claim construction disputes. See Vitronics, 90 F.3d at 1583. Courts should not rely on extrinsic evidence in claim construction to contradict the meaning of claims discernable from examination of the claims, the written description, and the prosecution history. See Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1308 (Fed. Cir. 1999) (citing Vitronics, 90 F.3d at 1583). However, it is entirely appropriate "for a court to consult trustworthy extrinsic evidence to ensure that the claim construction it is tending to from the patent file is not inconsistent with clearly expressed, plainly apposite, and widely held understandings in the pertinent technical field." Id. Extrinsic evidence "consists of all evidence external to the patent and prosecution history, including expert and inventor testimony, dictionaries, and learned treatises." Phillips, 415 F.3d at 1317. All extrinsic evidence should be evaluated in light of the intrinsic evidence. Id. at 1319.

DISCUSSION1

The patent-in-suit, U.S. Patent No. 5,781,784 (the "`784 Patent"), relates to a memory controller for lowering the power consumption of solid state memories. Claim 12 of the `784 patent reads as follows, with the disputed claim language in bold:

I. Power Control Means

The parties agree that the term "power control means" is governed by 35 U.S.C. § 112 ¶ 6. "Section 112, paragraph 6, allows a patentee to recite a function to be performed as a claim limitation rather than reciting structure or materials for performing that function." Omega Eng., Inc. v. Raytek Corp., 334 F.3d 1314, 1321 (Fed. Cir. 2003). The construction of a means-plus-function limitation follows a two-step approach. First, the Court "must identify the claimed function, staying true to the claim language and the limitations expressly recited by the claims." Id. (internal citations omitted). Second, the Court must identify the corresponding structures in the written description that perform those functions. Id. A disclosed structure is corresponding "only if the specification or the prosecution history clearly links or associates that structure to the function recited in the claim." B. Braun Med., Inc. v. Abbott Labs., 124 F.3d 1419, 1424 (Fed. Cir. 1997). "In other words, the structure must be necessary to perform the claimed function." Omega Eng., Inc., 334 F.3d at 1321.

The parties agree that the function of the "power control means" is "supplying a variable voltage to the memory integrated circuit." The parties' dispute centers on the corresponding structures identified in the `784 patent's specification.4 Both parties agree that the PWM rate controller (27) is necessary to perform the function of "supplying a variable voltage to the memory integrated circuit," but they disagree about whether two additional structures — the power director (29), and the low pass filter (31) — are also required.

Optimum Power argues that only the PWM rate controller (27) is necessary to perform the function of "supplying a variable voltage to the memory integrated circuit" because the specification states that "[p]ower to the solid state memory is controlled using pulse width modulation (PWM) by a PWM rate controller 27." `784 patent at 3:58-59. Optimum Power argues that as described in the specification, the PWM rate controller (27) increases voltage to the solid state memory to approximately 3v when a refresh of the memory is to occur, and then decreases the voltage to the solid state memory in quiescent periods. Id. at 5:28-44 & Figs. 2a, 2b. Optimum Power argues that neither the power director (29) nor the low pass filter (31) is necessary to perform the function of supplying the variable voltage to the integrated circuit, but rather that both are used to further reduce power consumption in the preferred embodiment. Optimum Power argues that power director (29) is a switch for selecting between alternate power sources (BAT1 and BAT2), and nothing in the patent or its file history requires the presence of more than one power source. Thus, Optimum Power argues, in a single power source embodiment practicing the claims of the `784 patent, the power director (29) would not be necessary and the power would flow directly from the power source to PWM rate controller (27), which would supply the variable voltage to the solid state memory.

Optimum Power also contends that the low pass filter (31) also does not supply variable voltage to the solid state memory. Optimum Power argues that Apple's only argument for including this structure is that the low pass filter (31) is an intervening structure between PWM rate controller (27) and the integrated memory circuit (13), and Optimum Power asserts that the fact that varying voltage generated by the PWM rate controller (27) passes through the low pass filter (31) on its way to the solid state memory (13) does not in and of itself transform the low pass filter (31) into corresponding structure. Optimum Power asserts that the low pass filter (31) does not supply power, but instead filters out higher voltages.

Apple argues that the three structures are necessary because the power director (29) and the PWM rate controller (27) each provide a particular type of signal to the low pass filter (31), and the low pass filter (31) uses these signals, together with voltages from the main and backup batteries, to produce the operating voltage VCC used to power the memory integrated circuit (13). Apple cites this statement from the specification: "Voltages from the main and backup batteries, a select signal from the power director 29 and a pulse width modulation signal from the PWM rate controller 27 are all input to an external low pass filter 31." `784 patent at 3:62-65. Apple argues that the power director (29) generates a "select" signal to dictate which power source (BAT1 or BAT2) should be used to produce the memory's operating voltage VCC. The PWM rate controller (27) generates a pulse width modulation signal, which specifies a duty signal that dictates how frequently the voltage supplied to the memory integrated circuit should be "pulsed." Apple states that the low pass filter (31) receives these two signals (the pulse width modulation signal from the PWM rate controller (27) and the "select" signal from the power director (29)), as well as voltages from the power sources (BAT1 and BAT2), and then produces the voltage VCC used to power the memory integrated circuit (13). Apple argues that all three components are required in order to supply a variable voltage to the memory integrated circuit because the PWM rate controller (27) does not generate the voltage used to power the memory; the voltage is generated by batteries BAT1 and BAT2. Apple argues that the PWM rate controller (27) is insufficient to perform the claimed function of supplying a variable voltage to the memory integrated circuit because the PWM rate controller only generates a pulse width that specifies a duty cycle.

The Court concludes that the PWM rate controller (27), the power director (29), and the low pass filter (31) are all necessary to perform the function of "supplying a variable voltage to the memory integrated circuit." The specification provides,

Id. at 3:58-65. The PWM rate controller (27) cannot, on its own, supply a variable voltage to the memory. The power is "supplied" by one of the two batteries selected by the power director (29), and the PWM rate controller generates a pulse width modulation signal specifying a duty cycle. The low pass filter (31) receives the voltages from the power sources, the "select" signal from the power director (29), and the PWM signal from the PWM rate controller (27), and the low pass filter (31) then supplies the voltage VCC used to power the memory integrated circuit (13).

Further, the `784 patent does not disclose the PWM rate controller (27) as being connected to the memory integrated circuit (13). Figure 1 shows that the variable voltage supplied to the memory integrated circuit is created by the inputs provided to the low pass filter (31) — the PWM rate controller (27) and the power director (29). See id. at Fig. 1. The patent states that Figure 1 "is a block diagram of the dynamic power management device of the present invention." Id. at 2:14-15 (emphasis added). Although Optimum Power argues that the Court should not adopt limitations from the preferred embodiment, "[i]f a patentee chooses to disclose a single embodiment, then any means-plus-function claim limitation will be limited to the single disclosed structure and equivalents thereof." Mettler-Toledo, Inc. v. B-Tek Scales, LLC, 671 F.3d 1291, 1296 (Fed. Cir. 2012). The `784 patent discloses the single embodiment shown in Figure 1, and the patent does not disclose an embodiment where power director (29) and low pass filter (31) are not associated with the function of supplying a variable voltage to the memory integrated circuit (13).

Accordingly, the Court holds that the corresponding structures for the power control means are:

(1) a pulse width modulation (PWM) rate controller (27) to generate a pulse width modulation signal;

(2) a power director (29) to select between power sources; and

(3) a low pass filter (31) to filter the pulse width modulation signal.

II. Logic Control Means

The parties agree that the term "logic control means" is governed by 35 U.S.C. § 112 ¶ 6 and that the functions of this limitation are "generating address and control signals provided to the memory integrated circuit and . . . controlling the power control means."

A. Generating address and control signals provided to the memory integrated circuit

1. Address signals

The parties agree that the binary address generator (21) is necessary for the generation of address signals provided to the memory integrated circuit, but disagree about whether the encoder (25) and slew rate controller (17) are also required.

Apple argues that as shown in Figure 1 of the `784 patent, generation of the address signals provided to the memory integrated circuit ("ADDR" on (13)) requires three things: (1) the creation of a binary address by binary address generator (21), (2) the encoding of the binary address by encoder (25), and (3) minimizing the slew rate of the encoded address by slew rate controller (17). The resultant address signal is then provided to the memory integrated circuit. Apple also cites the specification, which states that "[b]inary addresses generated by the address generator 21 are Gray coded by an encoder 25 before being input into the slew rate controller 17 and to the solid state memory 13." `784 patent at 3:54-57. Apple argues that the three structures are necessary because (1) the binary address generator generates the "binary addresses in response to a request from the host or in response to a refresh timer block 23," id. at 3:46-48; (2) the encoder 25 is needed to gray code those binary addresses, id. at 3:54-57; and (3) a slew rate controller is necessary to prolong the voltage rise and fall time of the signal so that the address signals can be provided to the memory integrated circuit. Apple contends that the binary address generator alone is insufficient to perform the function of generating the address signals provided to the memory integrated circuit because it only generates a binary address, and it does not provide the address signal to the memory. Apple argues that the only embodiment disclosed in the `784 patent for generating the address signal provided to the memory requires a binary address generator, an encoder, and a slew rate controller. See id. at Fig. 1.

Optimum Power argues that only the binary address generator (21) is necessary because the specification states that "[a] binary address generator (21) generates binary addresses in response to a request from the host in response to a refresh timer block." Id. at 3:46-48. Optimum Power argues that the encoder 25 and the slew rate controller 17 have no role in generating address signals, and instead that the encoder provides further power reduction, and the slew rate controller simply controls the rate at which the signals already generated rise and fall.

The Court agrees with Apple that generating address signals provided to the memory integrated circuit requires the binary address generator (21), the encoder (25), and the slew rate controller (17). While the binary address generator generates the addresses, the specification provides that "[b]inary addresses generated by the address generator 21 are Gray coded by an encoder 25 before being input into the slew rate controller 17 and to the solid state memory 13." Id. at 3:54-57 (emphasis added). Figure 1 shows that the addresses generated by binary address generator (21) must pass through the encoder (25) and the slew rate controller (17) in order for the address signals to be provided to the memory integrated circuit (13). See id. at Fig. 1. As discussed supra, the patent states that Figure 1 "is a block diagram of the dynamic power management device of the present invention." Id. at 2:14-15 (emphasis added); see also Mettler-Toledo, Inc., 671 F.3d at 1296. In addition, the specification makes clear that the encoder (25) and the slew rate controllers are key elements of the dynamic power management device, as both are need to reduce power consumption. See id. at 3:39-46 ("The slew rates of all of the digital inputs to the solid state memory 13 are minimized using slew rate controllers 15, 17 and 19 to conserve power. . . . Further power consumption is achieved by Gray coding address inputs to the solid state memory 13.").

2. Control signals

The parties agree that the binary address generator (21) is necessary to create the control signals provided to the memory integrated circuit. See `784 patent at 4:29-31 ("The timing sequencer and arbitor generates all the necessary control signals for the solid state memory 13 including RAS, CAS and WE signals."). The parties disagree about whether the slew rate controller (19) is also required to perform that function.

Apple argues that generation of the control signals provided to the memory integrated circuit ("RAS/CAS/WE" on memory (13)) involves both the creation of a control signal and minimizing the slew rate of the control signal. Apple contends that the slew rate controller (19) is needed to prolong the voltage rise and fall times of the control signal so that the signal can be provided to the memory integrated circuit. Id. at 3:39-44 ("The slew rates of all of the digital inputs to the solid state memory 13 are minimized using slew rate controllers 15, 17 and 19 to conserve power. As previously mentioned, the slew rate controllers may be input drivers designed to have prolonged rise times and fall times in comparison to conventional input drivers."). Apple argues that the slew rate controller is a critical element of the `784 patent's "dynamic power management strategy" and needed to reduce power consumption.

Optimum Power emphasizes that the specification instructs that "[t]he timing sequencer and arbitor generates all the necessary control signals for the solid state memory 13 including RAS, CAS and WE signals." Id. at 4:29-31. Optimum Power argues that the slew rate controller (19) has no role in generating control signals, and that the slew rate controller simply controls the rate at which the signals rise and fall.

The Court agrees with Apple that the slew rate controller (19) is also required to generate the control signals provided to the memory integrated circuit (13). Figure 1 shows that the control signals must pass through the slew rate controller (19) in order to be provided to the memory integrated circuit (13). See id. at Fig. 1; see also id. at 3:39-41 ("The slew rates of all the digital inputs to the solid state memory 13 are minimized using slew rate controllers 15, 17 and 19 to conserve power.") (emphasis added). In addition, as discussed supra, the slew rate controller (19) is a key element to the device's power management strategy. See id. at 2:65-3:2 ("The dynamic power management device uses slew rate controllers, driver circuits designed to have voltage rise and fall times prolonged in comparison to those of usual driver circuits, in order to reduce the slew rate and hence power consumption.").

B. Controlling the power control means

The logic control means' second function is "controlling the power control means." The parties agree that the A/D converter (33), power feedback block (35), and timing sequencer and arbitor (37) are structures necessary to the logic control means "for controlling said power means." The dispute centers on whether the power director (29) is also necessary for controlling the power control means.

Apple contends that the power director (29) is required to control the power means because the logic control means controls the power control means through closed-loop monitoring, and the specification states "[c]losed-loop power monitoring is performed by the power director 29, an A/D converter 33 and a power feedback block 35 under the control of a timing sequencer and arbitor 37." `784 patent at 4:9-11. Apple argues that these structures control the power control means as follows. The power director (29) receives voltages from each of the power sources (BAT1, BAT2), in addition to receiving the voltage to be used to power the memory integrated circuit 13. Id. at 4:12-13 ("The power director 29 receives voltages from each of the power sources in addition to the controlled voltage VCC."). The timing sequencer and arbitor (37) selects which voltage should be provided by the power director (29) and sampled using the A/D converter (33). Id. at 4:15-18 ("The foregoing voltages are input to an analog multiplexer or other analog switch and are selected in turn by the timing sequencer and arbitor 37 to be sampled using the A/D converter 33."). The A/D converter (33) then converts the analog voltage provided by the power director (29) to a digital representation, and the digital representation is provided to a power feedback device (35), which compares the digital representation of the selected voltage with a voltage required by the memory integrated circuit (13) in a particular mode of operation. Id. at 4:18-22. The power feedback device (35) notifies the timing sequencer and arbitor (37) whether or not the selected voltage is sufficient for the desired operation. Id. at 4:22-25. If the selected voltage is not sufficient for the operation of the memory (13), the timing sequencer and arbitor (37) can increase the pulse width duty cycle of the PWM rate controller (27), which is used to increase the power supplied to the memory, or instruct the power director to select another power source. Id. When power is insufficient, the timing sequencer and arbitor (37) delays the control signals that initiate an operation until adequate power has been confirmed.

Optimum Power contends that the power director (29) is only relevant in an embodiment where there are multiple power sources. Optimum Power argues that in a single power source embodiment, there would be no need to have a switch between alternative power supplies because VCC and voltage from the source would flow directly into timing sequencer and arbitor (37).

The Court concludes that the power director (29), in addition to the A/D converter (33), the power feedback device (35), and the timing sequencer and arbitor (37), is required to control the power control means. Optimum Power does not dispute that the logic control means controls the power control means through closed-loop monitoring. The specification states that "[c]losed-loop monitoring ensures that an adequate voltage is supplied to the solid state memory 13," id. at 4:26-28, and that "[c]losed-loop power monitoring is performed by the power director 29, an A/D converter 33 and a power feedback block 35 under the control of a timing sequencer and arbitor 37." Id. at 4:9-11. The patent further states that "[t]he power director 29 receives voltages from each of the power sources in addition to the controlled voltage VCC. . . . The foregoing voltages are input to an analog multiplexer or other analog switch and are selected in turn by the timing sequencer and arbitor 37 to be sampled using the A/D converter 33." Id. at 4:12-18. Although Optimum Power asserts that the power director (29) is not necessary in a single power source embodiment, the patent does not describe an embodiment with only one power source, nor does the patent disclose an embodiment where closed-loop monitoring can be performed without the power director (29). See Mettler-Toledo, Inc., 671 F.3d at 1296.

Accordingly, the Court holds that the corresponding structures for the logic control means are the following:

(1) a binary address generator (21) to generate binary addresses in response to a request from the host or in response to a refresh timer;

(2) an encoder (25) to Gray code the binary addresses;

(3) a slew rate controller (17 and 19) to prolong the voltage rise and fall times of the inputs to the memory integrated circuit in order to reduce power consumption;

(4) a timing sequencer and arbitor (37) to (a) generate control signals for the memory, (b) control closed loop power monitoring by selecting in turn voltages to be sampled by an A/D converter and, if the selected voltage is not sufficient for the operation of the memory, increasing the pulse width cycle of the PWM rate controller or selecting another power source, and (c) when the power is insufficient, delay the control signals that initiate an operation until adequate power has been confirmed;

(5) a power director (29) to receive voltages from each power source in addition to the voltage to be used to power the memory integrated circuit;

(6) an A/D converter (33) to convert the analog voltage provided by the power director to a digital representation; and

(7) a power feedback device (35) to compare the digital representation of the selected voltage with a voltage required by the memory integrated device in a particular mode of operation and to notify the timing sequencer and arbitor whether or not the selected voltage is sufficient for the desired operation.

III. Wherein the power control means supply power to said memory integrated circuit

In the claim construction briefing, Optimum Power proposed that this term be construed as "the power control means provides power to the memory integrated circuit," and Apple proposed "wherein the power control means supply power specifically to the memory integrated circuit without varying the power level or voltage supplied to the rest of the electronic system in which the device and memory integrated circuit is embedded."

However, at the claim construction hearing, in response to questioning from the Court, both parties stated that they agreed with the following construction: "wherein the power control means can supply power specifically to the memory integrated circuit without varying the power level or voltage supplied to the rest of the electronic system in which the device and memory integrated circuit is embedded." The Court finds that this construction is supported by the patent's intended memory-specific power management approach, in which the power supplied to the memory can be varied without varying the power supplied to any other components in the system. This construction is also consistent with the prosecution history. See Raffetto Decl. Ex. B at 30 (July 24, 2997 response, stating "Claims 1 and 23 . . . disclose varying the power level supplied to a memory without necessarily varying the power level supplied to the rest of the system components.") (emphasis in original); see id. at 11 (January 4, 1995 response, stating "Figure 1 clearly shows that the VCC input of DRAM 13 is coupled only to power director 29 (through low pass filter 31). Consequently, power director 29 can vary the voltage supplied to DRAM 13 without varying the voltage supplied to the rest of the electronic system in which power management device and DRAM is embedded.") (emphasis added).

Accordingly, the Court construes this phrase as "wherein the power control means can supply power specifically to the memory integrated circuit without varying the power level or voltage supplied to the rest of the electronic system in which the device and memory integrated circuit is embedded."

IV. Memory integrated circuit

Optimum Power contends that "memory integrated circuit" should be construed as "solid state memory," while Apple contends that the term should be defined as "a memory chip." Optimum Power argues that Apple's proposed construction limits the term to the preferred embodiment in which the dynamic power management device and the memory are on separate chips, and Optimum cites the specification, which states "Preferably, the power management device 10 is realized predominantly as a single integrated circuit. In Fig. 1, blocks to the left of the dashed vertical line are preferably realized on a single chip." `784 patent at 3:35-38. Optimum Power argues that the memory and dynamic power management device could be realized upon a single chip.

Apple argues that its proposed construction is based on the specification's repeated references to driving the inputs (e.g., address inputs) to "memory chips." See id. at 2:61-62. Apple notes that the specification states that "in order to minimize the power consumed by multiple chips, data is stored into and read out of the chips serially with tens or even hundreds of consecutive bytes being stored on a single chip, such that only one chip needs to be active at any given time, thus reducing power consumption." Id. at 3:4-9. Apple argues that these citations do not relate to a specific embodiment such as a DRAM, but rather that these citations are from the patent's discussion of the claimed device's "dynamic power management strategy." Apple also argues that Optimum Power's proposed construction is circular because the antecedent basis for the term being construed, "memory integrated circuit," is "solid state memory integrated circuit."

The Court concludes that Optimum Power's proposed construction, though redundant, is supported by the intrinsic evidence because the specification repeatedly refers to the memory integrated circuit as the "solid state memory." While Apple's proposed construction is not limited to a specific embodiment such as DRAM, it is limited to an embodiment in which the memory integrated circuit is on one chip and the power management device is on a separate chip. Although the patent states that such embodiment is preferable, there is nothing in the patent that limits the patent to a dual chip embodiment. See Phillips, 415 F.3d at 1323; cf. Mettler-Toledo, Inc., 671 F.3d at 1296 (in construing means-plus-function claim, corresponding structures are those disclosed in sole embodiment).

Accordingly, the Court construes "memory integrated circuit" as "solid state memory."

V. Variable voltage level

Optimum Power proposes that "variable voltage level" means "voltage that varies during a particular period or limitation," while Apple contends that this term should be construed as "a voltage that is cycled continuously between two different voltage values."

Apple argues that its construction is supported by the amendments and arguments that the applicant made to the PTO in order to overcome a prior art rejection. Towards the end of the prosecution of the `784 patent, the claims included a power control means for supplying a variable voltage to said memory integrated circuit, "wherein the power control means supply power to said memory integrated circuit at a first level during periods of no data access activity and at a second level during periods of data access activity . . ." Raffetto Decl. Ex. B at 13-15. The PTO rejected these claims as being anticipated by prior art reference Nakatani (U.S. Patent No. 5,297,098), which disclosed supplying a variable voltage to memory at a first level or a second level. Id. at 18. In its July 24, 1997 response (which resulted in the issuance of the `784 patent), the applicant amended the claims, in relevant part, as follows: "wherein the power control means supply power to said memory integrated circuit, said power being supplied to the memory integrated circuit at a first variable voltage level during periods of no data access activity and at a second variable voltage level during periods of data access activity, [a] the variable voltage supplied at said first variable voltage level being less than [a] the variable voltage supplied at said second variable voltage level." Id. at 28 (emphasis in original, showing amendments). The applicant distinguished Nakatani as follows:

Id. at 28-29.

Apple also argues that the distinction that the applicant was drawing can be seen by comparing the figures from Nakatani and the `784 patent. Compare Raffetto Decl. Ex. C, Fig. 3 (Nakatani), with `784 Patent, Figs. 2a & 2b. Figure 3 of Nakatani shows the voltage supplied during a period of data access activity (VCC) as being fixed or constant and the voltage supplied during a period of no data access activity (VDR) as also being fixed or constant. In contrast, Figure 2a of the `784 patent shows the voltage during a period of no data access activity (standby) as cycling between two different voltage values.

Optimum Power argues that the portion of the `784 patent's file history upon which Apple relies states that the claimed invention discloses dynamically variable voltage levels that "vary continuously during transition periods," and that the varying voltage described in this passage is the voltage during transition periods. Optimum Power also argues that defendant's reliance on the quiescent state's varying voltage between 1.5v and 2v to support its "cycled continuously between two different voltage values" limitation ignores the fact that during active periods, the voltage does not similarly vary on a fixed periodic basis. Optimum Power states that during periods of activity, the voltage varies between approximately 3v and 3.3v, and that while this voltage varies, it does not cycle continuously between 3v and 3.3v. See `784 patent at 5:40-44 ("about 3v, sufficient to perform a refresh operation"); id. at 6:6-7 ("[d]uring refresh voltage varies to about 3.3v").

The Court adopts Optimum Power's construction and finds that Apple's proposed construction imposes the additional limitation of cycling continuously between two different voltage levels that is neither required by the specification nor the file history. The specification states that the voltage varies during different modes of operation, but does not provide that the voltage cycles continuously between two different voltage values during each of those modes of operation. The specification states "During a standby mode of operation shown in FIG. 2b, the voltage cycles between approximately 1.5 volts and 2 volts." Id. at 5:28-31. Then, "[i]n preparation for a refresh cycle during a Prepare Refresh period shown in FIG. 2b, the duty cycle of the pulse width modulation signal is increased, causing the voltage to ramp up from about 1.5 volts to about 3 volts. When the voltage has reached about 3v, sufficient to perform a refresh operation, the power feedback block 35 of FIG. 1 signals the timing sequencer and arbitor (37) that it may proceed with the FAS cycle, initiating refresh." Id. at 5:36-44. "During refresh, the voltage rises to about 3.3 volts." Id. at 6:7-8. In the portions of the file history that Apple cites, the applicant distinguished Nakatani's fixed voltage levels from the invention's variable voltage levels but did not state that the voltage was required to cycle continuously between two different voltage levels. Optimum Power's proposed construction is consistent with both the specification and the file history in that it requires the voltage to vary during a particular period.

Accordingly, the Court construes "variable voltage level" as "voltage that varies during a particular period or limitation."

VI. The power supplied at the first level is sufficient to preserve information . . . and the power supplied at the second level is sufficient to read and write information (Claims 1 and 23)

The parties have stipulated to the following construction of this term: "the power supplied at the first level is sufficient to maintain memory information during periods of no data access activity, but not to read and write information in the memory integrated circuit, and the power supplied at the second level is sufficient to read and write information in the memory integrated circuit." Docket No. 182.

CONCLUSION

For the foregoing reasons and for good cause shown, the Court hereby construes the claim terms as set forth in this order.

IT IS SO ORDERED.